CE149 - Generating Fractional Rate Signals: ADC Sampling, Interpolation, Decimation and Si3000

by Microchip Technology

CE149 - Generating Fractional Rate Signals: ADC Sampling, Interpolation, Decimation and Si3000

In this example, ADC is configured to sample (AN0) at 1 KHz rate and the converted data is assembled in a 32-sample buffer.

About this Code Example


In this example, ADC is configured to sample (AN0) at 1 KHz rate and the converted data is assembled in a 32-sample buffer. This input data is interpolated and decimated to change the sampling rate of the signal by a fractional amount.
Timer 3 is setup to time-out every 1 milliseconds (1 KHz rate) and the ADC will sample the incoming signal at a rate of 1KHz. On every Timer3 time-out (every Ts = 1 millisecs), the ADC module will stop sampling and trigger a 10-bit A/D conversion. At that time, the conversion process starts and completes Tc second= 12*Tad = 1.2 microcsecs. When the conversion is complete, the module starts sampling again. However, since Timer3 is already on and counting, about (Ts-Tc) secs later, Timer3 will expire again and trigger the next conversion. The DMA is configured in continuous, ping pong mode, such that after the DMA channel has read 32 samples into a buffer (BufferA/BufferB) a DMA interrupt is generated. These samples are subjected to interpolation  at an interpolation rate of 3 and anti-alia filtering using the composite FIRInterpolate function. The interpolated samples are then anti-alias filtering and decimated at a decimation rate of 2 using the composite FIRDecimate function from the DSP library. Mean while the DMA controller starts filling new ADC samples into buffer (BufferB/BufferA). Thus the two buffers are alternately filled and processed in a continuous loop.The resulting signal with a rate of 1.5KHz is fed to the Si3000 codec.

The ADC module clock time period is configured as Tad = Tcy*(ADCS+1) = (1/40M)*1 = 100 nanosecs with ADCS = 0. Hence the conversion time for 10-bit A/D is 12*Tad = 1.2 microsecs.

void initTmr3();
Timer 3 is configured to time-out at 1 KHz rate.

void initAdc1(void);
ADC module is set-up to convert AIN0 input using CH0 S/H on Timer 3 event in 10-bit mode.

void initDma0(void);
DMA channel 0 is confiured in ping-pong mode to move the converted data from ADC to DMA RAM on every sample/convert sequence.
It generates interrupt after every 32 sample transfer.

void __attribute__((__interrupt__)) _DMA0Interrupt(void);
DMA interrupt service routine sets up flags to perform multirate filtering on the data buffer.


void Si3000CodecStart(Si3000CodecHandle*);
void Si3000CodecInit(Si3000CodecHandle*, int*);
Si3000 initialization and start up functions.

void Si3000CodecWrite(Si3000CodecHandle*,int *, int);
Function to tranmit data through Si3000 codec

int Si3000CodecWriteBusy(Si3000CodecHandle*);
Function which helps to know if the Si3000 codec is busy transmitting data.

  • Current Version: 1.0.0
  • Updated: Jun 16, 2012
  • Downloads: 505
  • Rating: 0/5 (0 votes cast)
  • Status: Released
    • MPLAB Version: V8.xx or above
    • C Compiler: MCC18 v3.30 or above
    • Development Tools: dsPICDEM 1.1 Plus development board
    • Supported Devices: dsPIC33FJ256GP710

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    Release History

    CE149 - Generating Fractional Rate Signals: ADC Sampling, Interpolation, Decimation and Si3000  (current version) June 15, 2012
    First Release to ECS